Felisp
84436a5ae0
http://my.svgalib.org/svgalib/svgalib-1.9.25.tar.gz http://my.svgalib.org/svgalib/
481 lines
12 KiB
C
481 lines
12 KiB
C
/* ATI Mach64 Driver for SVGALIB - (Driver (C) 1996 Asad F. Hanif)
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Ye olde defines
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*/
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/* Mach64 io and memory mapped registers */
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/* ripped from ati sdk */
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/* NON-GUI IO MAPPED Registers */
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#define ioCRTC_H_TOTAL_DISP 0x02EC
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#define ioCRTC_H_SYNC_STRT_WID 0x06EC
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#define ioCRTC_V_TOTAL_DISP 0x0AEC
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#define ioCRTC_V_SYNC_STRT_WID 0x0EEC
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#define ioCRTC_VLINE_CRNT_VLINE 0x12EC
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#define ioCRTC_OFF_PITCH 0x16EC
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#define ioCRTC_INT_CNTL 0x1AEC
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#define ioCRTC_GEN_CNTL 0x1EEC
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#define ioOVR_CLR 0x22EC
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#define ioOVR_WID_LEFT_RIGHT 0x26EC
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#define ioOVR_WID_TOP_BOTTOM 0x2AEC
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#define ioCUR_CLR0 0x2EEC
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#define ioCUR_CLR1 0x32EC
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#define ioCUR_OFFSET 0x36EC
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#define ioCUR_HORZ_VERT_POSN 0x3AEC
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#define ioCUR_HORZ_VERT_OFF 0x3EEC
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#define ioSCRATCH_REG0 0x42EC
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#define ioSCRATCH_REG1 0x46EC
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#define ioCLOCK_SEL_CNTL 0x4AEC
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#define ioBUS_CNTL 0x4EEC
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#define ioMEM_CNTL 0x52EC
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#define ioMEM_VGA_WP_SEL 0x56EC
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#define ioMEM_VGA_RP_SEL 0x5AEC
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#define ioDAC_REGS 0x5EEC
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#define ioDAC_CNTL 0x62EC
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#define ioGEN_TEST_CNTL 0x66EC
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#define ioCONFIG_CNTL 0x6AEC
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#define ioCONFIG_CHIP_ID 0x6EEC
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#define ioCONFIG_STAT0 0x72EC
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#define ioCONFIG_STAT1 0x76EC
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/* NON-GUI MEMORY MAPPED Registers - expressed in BYTE offsets */
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#define mCRTC_H_TOTAL_DISP 0x0000
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#define mCRTC_H_SYNC_STRT_WID 0x0004
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#define mCRTC_V_TOTAL_DISP 0x0008
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#define mCRTC_V_SYNC_STRT_WID 0x000C
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#define mCRTC_VLINE_CRNT_VLINE 0x0010
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#define mCRTC_OFF_PITCH 0x0014
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#define mCRTC_INT_CNTL 0x0018
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#define mCRTC_GEN_CNTL 0x001C
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#define mOVR_CLR 0x0040
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#define mOVR_WID_LEFT_RIGHT 0x0044
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#define mOVR_WID_TOP_BOTTOM 0x0048
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#define mCUR_CLR0 0x0060
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#define mCUR_CLR1 0x0064
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#define mCUR_OFFSET 0x0068
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#define mCUR_HORZ_VERT_POSN 0x006C
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#define mCUR_HORZ_VERT_OFF 0x0070
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#define mSCRATCH_REG0 0x0080
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#define mSCRATCH_REG1 0x0084
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#define mCLOCK_SEL_CNTL 0x0090
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#define mBUS_CNTL 0x00A0
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#define mMEM_CNTL 0x00B0
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#define mMEM_VGA_WP_SEL 0x00B4
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#define mMEM_VGA_RP_SEL 0x00B8
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#define mDAC_REGS 0x00C0
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#define mDAC_CNTL 0x00C4
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#define mGEN_TEST_CNTL 0x00D0
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#define mCONFIG_CHIP_ID 0x00E0
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#define mCONFIG_STAT0 0x00E4
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#define mCONFIG_STAT1 0x00E8
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/* GUI MEMORY MAPPED Registers */
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#define mDST_OFF_PITCH 0x0100
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#define mDST_X 0x0104
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#define mDST_Y 0x0108
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#define mDST_Y_X 0x010C
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#define mDST_WIDTH 0x0110
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#define mDST_HEIGHT 0x0114
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#define mDST_HEIGHT_WIDTH 0x0118
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#define mDST_X_WIDTH 0x011C
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#define mDST_BRES_LNTH 0x0120
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#define mDST_BRES_ERR 0x0124
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#define mDST_BRES_INC 0x0128
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#define mDST_BRES_DEC 0x012C
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#define mDST_CNTL 0x0130
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#define mSRC_OFF_PITCH 0x0180
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#define mSRC_X 0x0184
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#define mSRC_Y 0x0188
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#define mSRC_Y_X 0x018C
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#define mSRC_WIDTH1 0x0190
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#define mSRC_HEIGHT1 0x0194
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#define mSRC_HEIGHT1_WIDTH1 0x0198
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#define mSRC_X_START 0x019C
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#define mSRC_Y_START 0x01A0
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#define mSRC_Y_X_START 0x01A4
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#define mSRC_WIDTH2 0x01A8
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#define mSRC_HEIGHT2 0x01AC
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#define mSRC_HEIGHT2_WIDTH2 0x01B0
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#define mSRC_CNTL 0x01B4
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#define mHOST_DATA0 0x0200
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#define mHOST_DATA1 0x0204
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#define mHOST_DATA2 0x0208
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#define mHOST_DATA3 0x020C
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#define mHOST_DATA4 0x0210
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#define mHOST_DATA5 0x0214
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#define mHOST_DATA6 0x0218
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#define mHOST_DATA7 0x021C
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#define mHOST_DATA8 0x0220
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#define mHOST_DATA9 0x0224
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#define mHOST_DATAA 0x0228
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#define mHOST_DATAB 0x022C
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#define mHOST_DATAC 0x0230
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#define mHOST_DATAD 0x0234
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#define mHOST_DATAE 0x0238
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#define mHOST_DATAF 0x023C
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#define mHOST_CNTL 0x0240
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#define mPAT_REG0 0x0280
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#define mPAT_REG1 0x0284
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#define mPAT_CNTL 0x0288
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#define mSC_LEFT 0x02A0
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#define mSC_RIGHT 0x02A4
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#define mSC_LEFT_RIGHT 0x02A8
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#define mSC_TOP 0x02AC
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#define mSC_BOTTOM 0x02B0
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#define mSC_TOP_BOTTOM 0x02B4
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#define mDP_BKGD_CLR 0x02C0
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#define mDP_FRGD_CLR 0x02C4
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#define mDP_WRITE_MASK 0x02C8
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#define mDP_CHAIN_MASK 0x02CC
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#define mDP_PIX_WIDTH 0x02D0
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#define mDP_MIX 0x02D4
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#define mDP_SRC 0x02D8
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#define mCLR_CMP_CLR 0x0300
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#define mCLR_CMP_MASK 0x0304
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#define mCLR_CMP_CNTL 0x0308
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#define mFIFO_STAT 0x0310
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#define mCONTEXT_MASK 0x0320
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#define mCONTEXT_LOAD_CNTL 0x0324
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#define mGUI_TRAJ_CNTL 0x0330
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#define mGUI_STAT 0x0338
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/*
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Shortened register names
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*/
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#define IOBASE_ADDRESS 0x02ec
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#define IOB IOBASE_ADDRESS
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#define CRTC_H_TOTAL ( IOB + 0x0000 )
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#define CRTC_H_DISP ( IOB + 0x0002 )
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#define CRTC_H_SYNC_STRT ( IOB + 0x0400 )
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#define CRTC_H_SYNC_DLY ( IOB + 0x0401 )
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#define CRTC_H_SYNC_WID ( IOB + 0x0402 )
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#define CRTC_V_TOTAL ( IOB + 0x0800 )
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#define CRTC_V_DISP ( IOB + 0x0802 )
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#define CRTC_V_SYNC_STRT ( IOB + 0x0c00 )
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#define CRTC_V_SYNC_WID ( IOB + 0x0c02 )
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#define CRTC_OFFSET ( IOB + 0x1400 )
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#define CRTC_PITCH ( IOB + 0x1402 )
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#define CRTC_INT_CNTL ( IOB + 0x1800 )
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#define CRTC_GEN_CNTL ( IOB + 0x1c00 )
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#define CRTC_DBL_SCAN_EN 0x01
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#define CRTC_INTERLACE_EN 0x02
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#define CRTC_HSYNC_DIS 0x04
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#define CRTC_VSYNC_DIS 0x08
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#define CRTC_CSYNC_EN 0x10
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#define CRTC_PIX_BY_2_EN 0x20
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#define CRTC_BLANK 0x40
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#define CRTC_PIX_WIDTH ( IOB + 0x1c01 )
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#define PIX_WIDTH8 0x02
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#define CRTC_FIFO ( IOB + 0x1c02 )
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#define CRTC_EXT_DISP ( IOB + 0x1c03 )
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#define CRTC_EXT_DISP_EN 0x01
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#define CRTC_EXT_EN 0x02
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#define OVR_CLR_8 ( IOB + 0x2000 )
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#define OVR_CLR_B ( IOB + 0x2001 )
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#define OVR_CLR_G ( IOB + 0x2002 )
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#define OVR_CLR_R ( IOB + 0x2003 )
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#define OVR_WID_LEFT ( IOB + 0x2400 )
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#define OVR_WID_RIGHT ( IOB + 0x2402 )
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#define OVR_WID_TOP ( IOB + 0x2800 )
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#define OVR_WID_BOTTOM ( IOB + 0x2802 )
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#define SCRATCH_REG0 ( IOB + 0x4000 )
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#define TEST_MEM_ADDR ( IOB + 0x4000 )
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#define SCRATCH_REG1 ( IOB + 0x4400 )
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#define TEST_MEM_DATA ( IOB + 0x4400 )
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#define CLOCK_CNTL ( IOB + 0x4800 )
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#define FS2_bit 0x04
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#define FS3_bit 0x08
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#define CLOCK_SEL 0x0f
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#define CLOCK_DIV 0x30
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#define CLOCK_DIV1 0x00
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#define CLOCK_DIV2 0x10
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#define CLOCK_DIV4 0x20
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#define CLOCK_STROBE 0x40
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#define CLOCK_SERIAL_DATA 0x80
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#define BUS_CNTL1_16 ( IOB + 0x4c00 )
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#define BUS_CNTL2_16 ( IOB + 0x4c02 )
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#define MEM_CNTL8 ( IOB + 0x5000 )
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#define MEM_VGA_WP_SEL ( IOB + 0x5400 )
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#define MEM_VGA_RP_SEL ( IOB + 0x5800 )
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#define MEM_BNDRY ( IOB + 0x5002 )
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#define MEM_BNDRY_256K 0x01
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#define MEM_BNDRY_512K 0x02
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#define MEM_BNDRY_1M 0x03
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#define MEM_BNDRY_EN 0x04
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#define DAC_W_INDEX ( IOB + 0x5c00 )
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#define DAC_DATA ( IOB + 0x5c01 )
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#define DAC_MASK ( IOB + 0x5c02 )
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#define DAC_R_INDEX ( IOB + 0x5c03 )
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#define DAC8_W_INDEX ( DAC_W_INDEX & 0xff )
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#define DAC8_DATA ( DAC_DATA & 0xff )
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#define DAC8_MASK ( DAC_MASK & 0xff )
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#define DAC8_R_INDEX ( DAC_R_INDEX & 0xff )
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#define DAC_CNTL1 ( IOB + 0x6000 )
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#define DAC_EXT_SEL_RS2 0x01
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#define DAC_EXT_SEL_RS3 0x02
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#define DAC_CNTL2 ( IOB + 0x6001 )
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#define DAC_8BIT_EN 0x01
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#define DAC_PIX_DLY_MASK 0x06
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#define DAC_PIX_DLY_0NS 0x00
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#define DAC_PIX_DLY_2NS 0x02
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#define DAC_PIX_DLY_4NS 0x04
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#define DAC_BLANK_ADJ_MASK 0x18
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#define DAC_BLANK_ADJ_0 0x00
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#define DAC_BLANK_ADJ_1 0x08
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#define DAC_BLANK_ADJ_2 0x10
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#define DAC_TYPE_ ( IOB + 0x6002 )
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#define GEN_TEST_CNTL ( IOB + 0x6400 )
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#define CONFIG_CNTL ( IOB + 0x6800 )
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#define CONFIG_CHIP_ID ( IOB + 0x6c00 )
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#define CONFIG_STAT ( IOB + 0x7000 )
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#define GEN_TEST_CNTL ( IOB + 0x6400 )
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#define GEN_TEST_CNTL2 ( IOB + 0x6402 )
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#define PIXEL_DELAY_ON 0x0800
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#define PITCH_INFO (SCRATCH_REG1 + 2)
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#define DAC_VGA_MODE 0x80
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#define SET_VGA_MODE 0x02
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#define PITCH_INFO_PSIZE 0xc0
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#define PITCH_INFO_DAC 0x10
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#define PITCH_INFO_MUX2 0x20
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#define PITCH_INFO_TIOCLK 0x08
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#define PITCH_INFO_DAC0 0x01
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#define VGA_MODE 1
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#define ACCELERATOR_MODE 0
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#define DOTCLK_TOLERANCE 25
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#define REPORT
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#define DEBUG
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#define BAILOUT
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#define TRUE 1
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#define FALSE 0
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#define ATIPORT 0x1ce
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#define ATIOFF 0x80
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#define ATISEL(reg) (ATIOFF+reg)
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#define M64_BIOS_SIZE 0x8000
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#define M64_CLOCK_MAX 0x0f
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#define BPP_4 1
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#define BPP_8 2
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#define BPP_15 3
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#define BPP_16 4
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#define BPP_24 5
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#define BPP_32 6
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#define VRAM_MASK 0x66
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#define C_ISC2595 1
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#define C_STG1703 2
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#define C_CH8398 3
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#define C_BEDROCK 4
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#define C_ATT20C408 5
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#define C_RGB514 6
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#define D_ATI68860 5
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#define SAY(x) fprintf(stderr,#x"\n");fflush(stderr);
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#define DUMP(x) for (DUMPINDEX=0;DUMPINDEX<32;DUMPINDEX++) \
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DUMPOUT[31-DUMPINDEX]=(((x)>>DUMPINDEX)&0x1)? \
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'1':'0'; \
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DUMPOUT[32]='\0'; \
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printf("%s\n",DUMPOUT);
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typedef unsigned char UB;
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typedef unsigned short US;
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typedef unsigned long UL;
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typedef struct {
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UB h_disp; /* horizontal res in chars */
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UB dacmask; /* supported dacs */
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UB ram_req; /* ram required */
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UB max_dot_clk; /* max dot clock */
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UB color_depth; /* mac color depth */
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UB FILLER; /* make even #bytes */
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} M64_MaxColorDepth;
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typedef struct {
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UB ClockType; /* clock type */
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US MinFreq; /* min clock freq */
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US MaxFreq; /* max clock freq */
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US RefFreq; /* reference freq */
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US RefDivdr; /* reference freq divider */
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US N_adj; /* adjust */
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US Dram_Mem_Clk;
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US Vram_Mem_Clk;
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US Coproc_Mem_Clk;
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UB CX_Clk;
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UB VGA_Clk;
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UB Mem_Clk_Entry;
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UB SClk_Entry;
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US ClkFreqTable[M64_CLOCK_MAX*2]; /* clock frequency table */
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UB DefaultDivdr;
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UB DefaultFS2;
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UB CX_DMcycle;
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UB VGA_DMcycle;
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UB CX_VMcycle;
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UB VGA_VMcycle;
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} M64_ClockInfo;
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typedef struct {
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US Chip_Type; /* ASIC Chip type */
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UB Chip_Class; /* ASIC Chip class */
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UB Chip_Rev; /* ASIC Chip Revision */
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UB Chip_ID_Index; /* Name offset */
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UB Cfg_Bus_type; /* Bus type */
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UB Cfg_Ram_type; /* Ram type */
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UB Mem_Size; /* Memory installed */
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UB Dac_Type; /* Dac type */
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UB Dac_Subtype; /* Dac sub type */
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} M64_StartUpInfo;
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static UB *M64_Chip_Name[]={"GX-C","GX-D","GX-E","GX-F","GX-?",
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"CX","CX-?",
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"CT","ET",
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"?"};
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static UB *M64_Bus_Name[]={"ISA","EISA","","","","","VLB","PCI"};
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static UB *M64_Dac_Name[]={"","TVP3020, RGB514","ATI68875","BT476/BT478",
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"BT481, ATT490, ATT491","ATI68860/ATI68880",
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"STG1700","SC15021, STF1702"};
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static UB *M64_Ram_Name[]={"DRAM (256Kx4)","VRAM (256x4,x8,x16)",
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"VRAM (256Kx16 short shift register)",
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"DRAM (256Kx16)","Graphics DRAM (256Kx16)",
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"Enhanced VRAM (256Kx4,x8,x16)",
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"Enhanced VRAM (256Kx16 short shift register)",
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""};
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static US M64_Mem_Size[]={512,1024,2048,4096,6144,8192,0,0};
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static UB *M64_Clock_Name[]={"","ISC2595","STG1703","CH8398",
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"BEDROCK","ATT20C408","RGB514"};
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static UB M64_BPP[]={-1,4,8,15,16,24,32,-1};
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/*
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Some misc. structures
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*/
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typedef struct {
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US VRes;
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US HRes;
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UB max_cdepth;
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UB req_cdepth;
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US fifo_vl;
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US pdot_clock;
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UB refresh_mask;
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UB vmode;
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US misc;
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UB h_total;
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UB h_disp;
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UB h_sync_strt;
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UB h_sync_wid;
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US v_total;
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US v_disp;
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US v_sync_strt;
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UB v_sync_wid;
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UB clock_cntl;
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US dot_clock;
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UB h_overscan_a;
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UB h_overscan_b;
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UB v_overscan_a;
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UB v_overscan_b;
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UB overscan_8;
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UB overscan_B;
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UB overscan_G;
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UB overscan_R;
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} CRTC_Table;
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#define MAX_CRTC_TABLE 1
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static CRTC_Table CRTC_tinfo[MAX_CRTC_TABLE]={
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/* 640x480 60 Hz NI */
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{ 0, 0, 0, 0, 0,
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0, 60, 0x12, PIXEL_DELAY_ON,
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/* 0x63, 0x4f, 0x52, 0x2c,
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0x020c, 0x01df, 0x01ea, 0x22,
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*/ 0x64, 0x50, 0x53, 0x02,
|
|
0x20d, 0x1e0, 0x1eb, 0x02,
|
|
0x00, 2518,
|
|
0x00, 0x00, 0x00, 0x00,
|
|
0x00, 0x00, 0x00, 0x00
|
|
}
|
|
};
|
|
|
|
|